Physical & Logical Attributes
Fundamental Memory Class: | DDR4 SDRAM |
Module Speed Grade: | DDR4-2666V downbin |
Base Module Type: | UDIMM (133,35 mm) |
Module Capacity: | 16 GB |
Reference Raw Card: | A3 (8 layers) |
JEDEC Raw Card Designer: | SK hynix |
Module Nominal Height: | 31 < H <= 32 mm |
Module Thickness Maximum, Front: | 1 < T <= 2 mm |
Module Thickness Maximum, Back: | T <= 1 mm |
Number of DIMM Ranks: | 1 |
Address Mapping from Edge Connector to DRAM: | Standard |
DRAM Device Package: | Standard Monolithic |
DRAM Device Package Type: | 78-ball FBGA |
DRAM Device Die Count: | Single die |
Signal Loading: | Not specified |
DRAM I/O Width: | 8 bits |
Column Addressing: | 10 bits |
Row Addressing: | 17 bits |
Bank Addressing: | 2 bits (4 banks) |
Bank Group Addressing: | 2 bits (4 groups) |
Programmed DRAM Density: | 16 Gb |
Calculated DRAM Density: | 16 Gb |
Number of DRAM components: | 8 |
DRAM Page Size: | 1 KB |
Primary Memory Bus Width: | 64 bits |
Memory Bus Width Extension: | 0 bits |
DRAM Post Package Repair: | Supported |
Soft Post Package Repair: | Supported |
DRAM Timing Parameters
Fine Timebase: | 0,001 ns |
Medium Timebase: | 0,125 ns |
CAS Latencies Supported: | 10T, 11T, 12T, 13T, 14T, 15T, 16T, 17T, 18T, 19T, 20T, 21T, 22T, 23T |
Minimum Clock Cycle Time (tCK min): | 0,750 ns (1333,33 MHz) |
Maximum Clock Cycle Time (tCK max): | 1,600 ns (625,00 MHz) |
CAS# Latency Time (tAA min): | 13,750 ns |
RAS# to CAS# Delay Time (tRCD min): | 13,750 ns |
Row Precharge Delay Time (tRP min): | 13,750 ns |
Active to Precharge Delay Time (tRAS min): | 32,000 ns |
Act to Act/Refresh Delay Time (tRC min): | 45,750 ns |
Normal Refresh Recovery Delay Time (tRFC1 min): | 350,000 ns |
2x mode Refresh Recovery Delay Time (tRFC2 min): | 260,000 ns |
4x mode Refresh Recovery Delay Time (tRFC4 min): | 160,000 ns |
Short Row Active to Row Active Delay (tRRD_S min): | 3,000 ns |
Long Row Active to Row Active Delay (tRRD_L min): | 4,900 ns |
Write Recovery Time (tWR min): | 15,000 ns |
Short Write to Read Command Delay (tWTR_S min): | 2,500 ns |
Long Write to Read Command Delay (tWTR_L min): | 7,500 ns |
Long CAS to CAS Delay Time (tCCD_L min): | 5,000 ns |
Four Active Windows Delay (tFAW min): | 21,000 ns |
Maximum Active Window (tMAW): | 8192*tREFI |
Maximum Activate Count (MAC): | Unlimited MAC |
DRAM VDD 1,20 V operable/endurant: | Yes/Yes |
Supply Voltage (VDD), Min / Typical / Max: | 1,16V / 1,20V / 1,26V |
Activation Supply Voltage (VPP), Min / Typical / Max: | 2,41V / 2,50V / 2,75V |
Termination Voltage (VTT), Min / Typical / Max: | 0,565V / 0,605V / 0,640V |
Intel Extreme Memory Profiles
Profiles Revision: 2.0 |
Profile 1 (Certified) Enabled: Yes |
Profile 2 (Extreme) Enabled: No |
Profile 1 Channel Config: 2 DIMM/channel |
XMP Parameter | Profile 1 | Profile 2 |
Speed Grade: | DDR4-4406 | N/A |
DRAM Clock Frequency: | 2200 MHz | N/A |
Module VDD Voltage Level: | 1,50 V | N/A |
Minimum DRAM Cycle Time (tCK): | 0,454 ns | N/A |
CAS Latencies Supported: | 19T | N/A |
CAS Latency Time (tAA): | 19T | N/A |
RAS# to CAS# Delay Time (tRCD): | 26T | N/A |
Row Precharge Delay Time (tRP): | 26T | N/A |
Active to Precharge Delay Time (tRAS): | 46T | N/A |
Active to Active/Refresh Delay Time (tRC): | 72T | N/A |
Four Activate Window Delay Time (tFAW): | 53T | N/A |
Short Activate to Activate Delay Time (tRRD_S): | 4T | N/A |
Long Activate to Activate Delay Time (tRRD_L): | 11T | N/A |
Normal Refresh Recovery Delay Time (tRFC1): | 771T | N/A |
2x mode Refresh Recovery Delay Time (tRFC2): | 573T | N/A |
4x mode Refresh Recovery Delay Time (tRFC4): | 353T | N/A |
Show delays in nanoseconds |