The above sequence will, on some architectures, result in a memory protection fault at step 2. However, via speculative execution, instructions 2, 3, and 4 will get executed, loading the cache with either A0u or A1u. The hardware will annul all "functional" consequences of instructions 2,3,4, as it should, when the fault gets detected, but the cached state of the speculatively fetched location will remain. The attacker then reads, via a previously-process or other standard mechanisms, "his" A0u and A1u, timing both accesses. This timing will determine which of the two locations is now in cache, and thus reveal the value of memory bit 0 at address Ap.
https://en.wikipedia.org/wiki/Meltdown_(security_vulnerability)