As an EE with my PhD (former Gigabyte board design lead, currently Intel Foundry lab manager), I will just say that this design is actually psychotic. I genuinely have to question the credentials and/or ethical abilities of whoever signed off on this.
This is what drove me out of the board design world back in the late 2000s. Cutting corners on components that need to be done right or else somebody gets hurt or killed. I saw the 8-pin and 6-pin get introduced in my time. They were good and I hated that smaller gauge options were even allowed. 12VHPWR and any of its iterations are a step backwards for this industry and a stain on the reputation of PCI SIG as a whole, but particularly Nvidia.
They are knowingly shaving down the safety margin on a cable this connector, with just under a 1.15x factor to the 660W absolute max rating of the cable, on top of cutting costs on board design for what can at most be a few dollars in components for a MINIMUM $2000 product. This is peak penny pinching behavior on the same order that put Intel where they are today, and I say that as somebody who's been here since Haswell. I've seen this game played before and you don't win it in the end.