It’s a chicken-and-egg issue. At the start of risk production, by definition there have been no customer designs put through the fab. Actually this is not quite true, Sun explained. Before the start of risk production the company has already run a number of shuttles with test chips from customers, so foundry and clients are already starting to wring out the more critical structures in the first customer designs. But these test shuttles are not full chips either.
So to convince themselves that the line is ready to take on a wafer full of real chips instead of a wafer full of test structures, TSMC develops an SRAM. As reported in a press release earlier this week, the vehicle for all three announced variants of the 28nm process—low-power with SiON gate stack, G with high-k/metal-gate, and LP with high-k/metal-gate–happens to be a 64Mbit part. TSMC says it now has yield at target performance for the SRAM on all three processes.
Running the SRAM vehicle through the fab is just one step in many, according to Sun. Before the SRAM goes through, and in fact before process freeze, TSMC runs test chips designed to stress each of the mandatory and recommended design rules. Information from these runs goes into the version of the rule deck that goes out with the first PDKs. From there on, work is more or less continuous as the process engineers work out issues, tune the process ever closer to the target performance and yield, and tweak the design rules. At some point in the schedule, the engineers judge the process ready to try full SRAM wafers.
https://www.edn.com/electronics-blo...C-risk-production-what-does-it-mean-for-28nm-
): Was wird man denn übereinander stapeln können? I/O unten, dazwischen vielleicht noch DRAM und oben müssen schon die PUs hin, also sowohl die CPU-Kerne als auch die GPU, sonst ist es thermisch kaum zu bändigen.
