On the architectural level, the biggest change is called Core Power Gating, something Intel introduced in Nehalem. The idea is simple, even when off, as long as power can get to a transistor, some of it will get around the gate and be lost. This is conventionally known as leakage, and has become one of the most troubling problems in modern chip building.
As process geometry shrinks, the silicon gates get smaller, and more electrons get through them. High-K Metal Gates improve this, but don’t stop leakage entirely. Until you stop electricity from getting to the transistors, they will always leak a little. A few hundred million ‘littles’ add up to light bulb territory for lost power and heat generated, something first postulated by Fermi if we recall correctly.
Intel and AMD have come up with a solution. They put a ring of transistors around the core itself, it is the black border labeled PG ring in the picture above. What it does is when a CPU goes into the new C6 sleep state, all internal data is saved to off-core DRAM, and the core is powered down completely.
It does not run slowly, the power gates turn off power to it entirely, and then those 110 million transistors stop leaking. This can be a huge power savings, AMD claims a 10-fold reduction in core leakage.