Falls es jemanden interessiert; der FSB 495 MHz beruht auf folgenden Einstellungen:
BIOS-Settings des DFI LANPARTY DK P45-T2RS Plus
BIOS v. 19.08.2009-D45PDA819
30.08.2009
CPU Feature Page
Thermal Management Control................Disabled
PPM (EIST) Mode............................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Disabled
Virtualization Technology.................Disabled
Core Multi-Processing.....................Enabled
Main BIOS Page
Exit Setup Shutdown......................Mode 2
Shutdown after AC loss....................Enabled
AC Shutdown free..........................Enabled
O.C. Fail Retry Counter...................1
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio........................... 8 x
CPU N/2 Ratio.............................Enabled
CPU Clock.................................495
Boot Up Clock.............................345
CPU Clock Amplitude....................... 700mV
CPU Clock0 Skew........................... 100ps
CPU Clock0 Skew........................... 100ps
DRAM Speed................................333/800=1190 MHz
PCIE Clock................................100MHz
CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
Voltage Setting Page
CPU VID Control......................... 100 mV
DRAM Voltage Control......................2.001 V
SB Core/CPU PLL Voltage...................1.55 V
NB Core Voltage...........................1.4075 V
CPU VTT Voltage...........................1.34 V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
CPU GTL 0/2 REF Volt......................0.67X
CPU GTL 1/3 REF Volt......................0.67X
North Bridge GTL REF Volt ................0.63X
FSB Vref.................................. 24
DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Disabled
Clock Setting Fine Delay..................
Flex Memory Mode..........................Auto
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................Auto
REF to ACT Delay (tRFC)...................60
Performance Level.........................8
Read Delay Phase Adjust...................Auto
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR).................Auto
ACT to ACT Delay (tRRD)...................Auto
Read to Write Delay (tRDWR)...............Auto
Ranks Write to Write (tWRWR)..............Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................Auto
ALL PRE to Refresh........................Auto
Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto
Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto
Clock Setting Fine Delay Page
DLL and RCOMP Settings .................ByMenu
Ch1 DRAM Default Skew.....................Model 3
Ch2 DRAM Default Skew.....................Model 3
RCOMP Setting.............................Model 1
Fine Delay Step Degree....................70ps
Ch1 Clock Crossing Setting................Nominal
DIMM 1 Clock fine delay...................Current 1924ps
DIMM 2 Clock fine delay...................Current 1924ps
Ch 1 Control0 fine delay..................Current 194ps
Ch 1 Control1 fine delay..................Current 194ps
Ch 1 Control2 fine delay..................Current 110ps
Ch 1 Control3 fine delay..................Current 96ps
Ch 1 Command fine delay...................Current 134ps
Ch2 Clock Crossing Setting................Nominal
DIMM 3 Clock fine delay...................Current 1924ps
DIMM 4 Clock fine delay...................Current 1882ps
Ch 2 Control0 fine delay..................Current 152ps
Ch 2 Control1 fine delay..................Current 152ps
Ch 2 Control2 fine delay..................Current 70ps
Ch 2 Control3 fine delay..................Current 56ps
Ch 2 Command fine delay...................Current 152ps
Ch1Ch2 CommonClock Setting................Nominal
Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto
Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto
Interessant war für mich festzustellen, dass durch eine Reduktion der CPU Clock Amp. von 800mV auf 700mV weniger Spannung auf die Nb und weniger VTT-Spannung mit höheren FSBsen bedingte.
Zuvor hatte ich die NB mit 1,43V und mehr befoiert bis das System stabil lief
Oi, Oi, Oi...