News Intel Comet Lake: Acht CPUs mit zwei bis sechs Kernen bei 4,5 bis 25 Watt
- Ersteller Volker
- Erstellt am
- Zur News: Intel Comet Lake: Acht CPUs mit zwei bis sechs Kernen bei 4,5 bis 25 Watt
Tech_Blogger
Banned
- Registriert
- Aug. 2019
- Beiträge
- 246
Weil ich normalerweise nicht immer die Lust habe nach dem Beleg zu suchen, deswegen!
Aber eigentlich hat es doch eh nichts gebracht, weil du bei deiner Meinung bleibst?
Aber eigentlich hat es doch eh nichts gebracht, weil du bei deiner Meinung bleibst?
MK one
Banned
- Registriert
- März 2017
- Beiträge
- 4.889
Ich akzeptiere nach wie vor die reine Belichtung nicht als Hinderungsgrund , es werden schließlich 1,2 Billionen Transistoren auf dem Wafer belichtet , es wird da wohl eher die einstellbare Maskengröße bei den derzeitigen Belichtungsmaschinen sein , was aber eher eine technische als physikalische Begrenzung ist .
https://wccftech.com/meet-cerebras-...ore-than-56-times-the-size-of-an-nvidia-v100/
The 400,000 cores on the WSE are connected via the Swarm communication fabric in a 2D mesh with 100 Pb/s of bandwidth. Swarm is a massive on-chip communication fabric that delivers breakthrough bandwidth and low latency at a fraction of the power draw of traditional techniques used to cluster graphics processing units. It is fully configurable; software configures all the cores on the WSE to support the precise communication required for training the user-specified model. For each neural network, Swarm provides a unique and optimized communication path.
The WSE has 18 GB of on-chip memory, all accessible within a single clock cycle, and provides 9 PB/s memory bandwidth. This is 3000x more capacity and 10,000x greater bandwidth than the leading competitor. More cores, more local memory enables fast, flexible computation, at lower latency and with less energy.
Yield and binning of the Cerebras WSE are going to be very interesting. For one, if you are using the entire wafer as a die, you are either going to get 100% yield if the design can absorb defects or 0% if it cannot. Clearly, since the prototypes were made, the design is capable of absorbing defects. In fact, the CEO stated that the design expects around 1% to 1.5% defects of the functional surface area and the microarchitecture simply reconfigures for the available cores. Furthermore, redundant cores are placed throughout the chip to minimize any performance loss. There is no information on binning right now but it goes without saying that this is the world’s most binnable design.
We are also told that the company had to design its own manufacturing and packaging science considering no tools are currently designed to handle a wafer-scale processor. Not only that, the software had to be rewritten to handle over 1 Trillion transistors in a single processor. Cerebras Systems is clearly a company that has incredible potential and seeing the splash they caused at Hot Chips we cannot wait to see some testing results from these Wafer Scale Engines.
https://wccftech.com/meet-cerebras-...ore-than-56-times-the-size-of-an-nvidia-v100/
The 400,000 cores on the WSE are connected via the Swarm communication fabric in a 2D mesh with 100 Pb/s of bandwidth. Swarm is a massive on-chip communication fabric that delivers breakthrough bandwidth and low latency at a fraction of the power draw of traditional techniques used to cluster graphics processing units. It is fully configurable; software configures all the cores on the WSE to support the precise communication required for training the user-specified model. For each neural network, Swarm provides a unique and optimized communication path.
The WSE has 18 GB of on-chip memory, all accessible within a single clock cycle, and provides 9 PB/s memory bandwidth. This is 3000x more capacity and 10,000x greater bandwidth than the leading competitor. More cores, more local memory enables fast, flexible computation, at lower latency and with less energy.
Yield and binning of the Cerebras WSE are going to be very interesting. For one, if you are using the entire wafer as a die, you are either going to get 100% yield if the design can absorb defects or 0% if it cannot. Clearly, since the prototypes were made, the design is capable of absorbing defects. In fact, the CEO stated that the design expects around 1% to 1.5% defects of the functional surface area and the microarchitecture simply reconfigures for the available cores. Furthermore, redundant cores are placed throughout the chip to minimize any performance loss. There is no information on binning right now but it goes without saying that this is the world’s most binnable design.
We are also told that the company had to design its own manufacturing and packaging science considering no tools are currently designed to handle a wafer-scale processor. Not only that, the software had to be rewritten to handle over 1 Trillion transistors in a single processor. Cerebras Systems is clearly a company that has incredible potential and seeing the splash they caused at Hot Chips we cannot wait to see some testing results from these Wafer Scale Engines.
Zuletzt bearbeitet:
Tech_Blogger
Banned
- Registriert
- Aug. 2019
- Beiträge
- 246
Das hab ich ja auch so nicht behauptet.
Aktuell geht halt nicht mehr, deswegen wurdem bei dem Chip mehrere "Dice" belichtet, die man dann einfach nur nicht zerschnitten hat.
Ähnliche Themen
