@duklum
Unnötig gegen AMD feuern ohne Plan haben wer gerne!
Skylake:
The major expected changes between the Haswell and Skylake architectures include the abandonment and removal of the fully integrated voltage regulator (FIVR) introduced with Haswell,[8] and the integration of the Platform Controller Hub (PCH) onto the die for Skylake's H, U and Y variants, effectively following a system-on-chip (SoC) design layout. The S variant will remain a two-chip design. On the variants that will use the PCH, Direct Media Interface (DMI) 2.0 will be replaced by DMI 3.0, which promises speeds of up to 8 GT/s.
Und anders machts auch AMD nicht SoC bei den Kleinen und mit Southbridge bei den Grösseren.
Unnötig gegen AMD feuern ohne Plan haben wer gerne!
Skylake:
The major expected changes between the Haswell and Skylake architectures include the abandonment and removal of the fully integrated voltage regulator (FIVR) introduced with Haswell,[8] and the integration of the Platform Controller Hub (PCH) onto the die for Skylake's H, U and Y variants, effectively following a system-on-chip (SoC) design layout. The S variant will remain a two-chip design. On the variants that will use the PCH, Direct Media Interface (DMI) 2.0 will be replaced by DMI 3.0, which promises speeds of up to 8 GT/s.
Und anders machts auch AMD nicht SoC bei den Kleinen und mit Southbridge bei den Grösseren.