Valhalla Common Options:
- Performance
- Core Watchdog:
1) Core Watchdog Timer Enable
2) Core Watchdog Timer Interval
3) Core Watchdog Timer Severity
Soc Miscellaneous Control:
* ABL Console Out Control
BIXBY Common Options
Local APIC Mode:
1) xAPIC
2) x2APIC
3) Auto
MCA error thresh enable
1) False
2) True
MCA error thresh count
SMU and PSP Debug Mode
1) Disabled
2) Enabled
3) Auto
Xtrig7 Workaround
1) Auto
2) No Workaround
3) Bronze Workaround
4) Silver Workaround
PPIN Opt-in
1) Disabled
2) Enabled
3)Auto
CCD/Core/Thread Enablement
* CCD Control:
1) Auto
2) 2 CCDs
3) 3 CCDs
4) 4 CCDs
5) 6 CCDs
or
* CCD Control:
1) Auto
2) 2 CCDs
3) 3 CCDs
4) 4 CCDs
or
* CCD Control:
1) Auto
2) 1 CCDs
Core control:
1) Auto
2) TWO (1 + 1)
3) FOUR (2 + 2)
4) SIX (3 + 3)
Link:
CAKE CRC perf bounds Control
CAKE CRC perf bounds
4-link xGMI max speed
3-link xGMI max speed
System probe filter
PSP error injection support
NUMA nodes per socket:
1) NPS0
2) NPS1
3) NPS2
4) NPS4
5) Auto
1TB remap:
1) Do not remap
2) Attempt
3) Auto
DRAM map inversion:
1) Disabled
2) Enabled
3) Auto
ACPI
*ACPI SRAT L3 Cache As NUMA Domain
- ACPI SLIT Distance Control
- ACPI SLIT remote relative distance
- ACPI SLIT virtual distance
- ACPI SLIT same socket distance
- ACPI SLIT remote socket distance
- ACPI SLIT local SLink distance
- ACPI SLIT remote SLink distance
- ACPI SLIT local inter-SLink distance
- ACPI SLIT remote inter-SLink distance
Common RAS
- DRAM Post Package Repair
- RCD Parity
- DRAM Address Command Parity Retry
- Max Parity Error Replay
- Write CRC Enable
- DRAM Write CRC Enable and Retry Limit
- Max Write CRC Error Replay
- Disable Memory Error Injection
ECC Configuration
* DRAM UECC Retry
Security
* Chipselect Interleaving:
1) Disabled
2) Auto
Address Hash CS
Address Hash Rm
Memory MBIST
* MBIST Test Mode:
1) Interface Mode
2) Data Eye Mode
3) Both
4) Auto
* MBIST Per Bit Slave Die Reporting
1) Disabled
2) Enabled
3) Auto
* Pattern Select
1) PRBS
2) SSO
3) Both
- Pattern Length
- Aggressor Channel
- Aggressor Static Lane Control
- Aggressor Static Lane Select Upper 32 bits
- Aggressor Static Lane Select Lower 32 Bits
- Aggressor Static Lane Select ECC
- Aggressor Static Lane Value
- Target Static Lane Control
- Target Static Lane Select Upper 32 bit
- Target Static Lane Select Lower 32 Bits
- Static Lane Select ECC
- Target Static Lane Value
- Data Eye Type:
1) 1D Voltage Sweep
2) 1D Timing Sweep
3) 2D Full Data Eye
4) Worst Case Margin Only
- Worst Case Margin Granularity
- Read Voltage Sweep Step Size
- Read Timing Sweep Step Size
- Write Voltage Sweep Step Size
- Write Timing Sweep Step Size
XFR Enhancement:
1) FCLK Frequency
2) MEMCLK Frequency
3) UCLK DIV1 MODE:
a) Auto
b) UCLK==MEMCLK
c) UCLK==MEMCLK/2
+ precision boost override
SMU Common Options
- CLDO_VDDP Control
- EfficiencyModeEn
- Package Power Limit Control
- DF Cstates
- Fixed SOC Pstate
- CPPC
NTB Common Options
* Link Speed : Gen 4